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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
FEATURES
* Outputs: * Two high frequency differential LVPECL outputs Output frequency: up to 700MHz * One LVCMOS/LVTTL VCXO PLL output with output enable * One Reference clock output with output enable * One LOCK detect output * Input mux supports 3 selectable inputs: one differential input pair and two LVCMOS/LVTTL input clocks * 13-bit VCXO PLL feedback and reference dividers provide wide range of frequency translation ratio options * FemtoClock frequency multiplier supports rate of: 560MHz - 700MHz * `Lock Detect' output reports lock status of VCXO PLL * VCXO PLL circuit provides jitter attenuation with loop bandwidth of 250Hz and below (user adjustable) * RMS phase jitter, random at 12kHz to 20MHz: <1ps (design target) * 3.3V supply voltage * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS843002-31 is a member of the HiperClockSTM family of high performance clock HiPerClockSTM solutions from ICS. This monolithic device is a high-performance, PLL-based synchronous clock generator and jitter attenuation circuit. The ICS843002-31 contains two clock multiplication stages that are cascaded in series. The first stage is a VCXO-based PLL that is optimized to provide reference clock jitter attenuation, to be jitter tolerant, and to provide a stable reference clock for the second multiplication stage. The second stage is the proprietary ICS FemtoClockTM circuit which is a high-frequency, sub-picosecond clock multiplier.
IC S
The VCXO PLL has an on-chip VCXO circuit that uses an external, inexpensive pullable crystal in the 17.5 to 25MHz range. The PLL includes 13 bit reference and feedback dividers supporting complex PLL multiplication ratios and input reference clock rates as low as 2.3kHz. External loop filter components are used (two resistors and two capacitors) to achieve the low loop bandwidth needed for jitter attenuation of a recovered data clock. The FemtoClock circuit can multiply the VCXO crystal frequency by a factor of 28 or 32 (selectable) and provide a clock output of up to 700MHz. Clock Input/Output Configuration: * Clock Inputs - one differential pair, two singled ended (mux selected) * Differential input pair can support LVPECL, LVDS, LVHSTL, SSTL, HCSL or single-ended LVCMOS or LVTTL levels * Singled ended inputs can support LVCMOS or LVTTL levels * Clock Outputs, FemtoClockS two LVPECL pairs (selectable output dividers) * Clock Output, VCXO - one single ended output (at VCXO crystal frequency) * Clock Output, other - VCXO reference clock Example Applications: * SONET/SDH line card clock generator (up to 622.08MHz for OC-48) using 8kHz frame clock as input reference * Jitter attenuation of a recovered communications clock * Complex-ratio clock frequency translation between various communication protocols, such as: * For telecom, OC-12 to E3 rate conversion, 622.08MHz to 34.368MHz, PLL ratio of 179/32 * For digital video, ITU-R601 to SMPTE 252M/59.94, 27MHz to 74.17582MHz, PLL ratio of 250/91
VCCA_XO XTAL_IN XTAL_OUT
PIN ASSIGNMENT
XOFB0 XOFB1 XOFB2 XOFB3 XOFB4 XOFB5 XOFB6 XOFB7 XOFB8 XOFB9 XOFB10 XOFB11
LF1 LF0 ISET VEE NV1 NV0 VCC MR CLK0 nCLK0 OE_REF CLK1 VCC SEL1 SEL0 CLK2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 64-Lead TQFP, EPAD 8 41 10mm x 10mm x 1.0mm 9 40 package body 10 39 Y package 11 38 Top View 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
XOFB12
ICS843002-31
VEE REF_CLK VCLK LOCK VCCO_CMOS nQB QB VEE nQA QA VCCO_PECL MP NPB0 NPB1 NPB2 VCCA
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843002CY-31
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1
XOIN12 XOIN11 XOIN10 XOIN9 XOIN8 XOIN7 XOIN6 XOIN5 XOIN4 XOIN3 XOIN2 XOIN1 XOIN0 NPA2 NPA1 NPA0
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
BLOCK DIAGRAM - NOMINAL SYSTEM CONFIGURATION
NPB[2:0] NPA[2:0] NV[1:0]
3 3 2 VCXO PLL Output Divider NV[1:0] 00: 01: 10: 11: /1 /12 /16 Disabled Drive Low QA Output Divider NPA[2:0] 000: 001: 010: 011: 100: 101: 110: 111: /1 /2 /4 /8 /12 /14 /16 Disabled Drive Low
ISET Charge Pump Current
VCLK
CLK0 nCLK0
00
External Loop Filter Connection 17.5 - 25MHz LF0 LF1
XTAL_OUT XTAL_IN
CLK1
01 Input Divider
CLK2
10
XOIN[12:0] /1 to /8191
VCXO PLL
FemtoClockTM Frequency Multiplier 0: x32 1: x28
QA nQA
11 Bypass VCXO PLL Feedback Divider
QB Output Divider NPB[2:0] 000: 001: 010: 011: 100: 101: 110: 111: QA /1 QA /2 QA /4 QA /8 XOIN Output OFB Output MP Output Disabled Drive Low
SEL1 SEL0 XOIN[12:0] XOFB[12:0] MP
13 13 >1 1
XOFB[12:0] /1 to /8191
QB nQB
REF_CLK OE_REF
LOCK Detect
LOCK
NOTE 1: For application configuration (non-test/bypass modes). NOTE 2: Bold lines are primary clock paths (non-control/non-feedback lines). Not all control lines and signal paths are shown in this simplified block diagram.
843002CY -31
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2
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
IN
SIMPLIFIED BLOCK DIAGRAM - CLOCK SIGNAL PATHS
BYPASS MODE
ISET Charge Pump Current External Loop Filter Connection 17.5 - 25MHz LF0 LF1 1 1 Bypass
VCXO PLL Output Divider NV[1:0] 00: 01: 10: 11: /1 /12 /16 Disabled Drive Low QA Output Divider NPA[2:0] NPA[2:0] 000: /1 001: /2 010: /4 011: /8 100: /12 101: /14 110: /16 111: Disabled Drive Low
VCLK
CLK0 nCLK0
XTAL_OUT
01 Input Divider XOIN[12:0] /1 to /8191
CLK1
XTAL_IN
VCXO PLL
FemtoClockTM Frequency Multiplier
QA nQA
CLK2
10
000: /1 001: /2 010: /4 011: /8 111: Disabled
QB nQB
SEL1 = 1 SEL0 = 1
VCXO PLL Feedback Divider XOFB[12:0] /1 to /8191
FemtoClockTM Feedback Divider MP 0: /32 1: /28 110: MP 101: XOFB 100: XOIN
NPB2 NPB1 NPB0
NOTE 1: Setting SEL1:SEL0 = 11 enables bypass mode. Only clock signals on the CLK0/nCLK0 input pair are routed to the device in bypass mode. NOTE 2: Bold lines show clock bypass paths. Not all control lines and signal paths are shown in this simplified block diagram.
843002CY-31
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3
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
Description Loop filter connection pins. Charge pump current setting pin. Negative supply pins. Normally connected to ground. VCXO PLL output divider control pins. Pullup LVCMOS/LVTTL interface levels. Core power supply pins. Master Reset. When HIGH, resets all internal dividers and Pulldown LVCMOS outputs are in high impedance. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. Pulldown VCC/2 bias voltage when left floating. Output enable control for reference clock output. When logic LOW, Pulldown the reference clock output is in high impedance. When logic HIGH, the output is enabled. LVCMOS/LVTTL interface levels. Pulldown Clock input. LVCMOS/LVTTL interface levels. Pulldown Input clock select. LVCMOS/LVTTL interface levels. Pulldown Clock input. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS (CONTINUED ON NEXT PAGE)
Number 1, 2 3 4, 41, 48 5, 6 7, 13 8 9 10 11 12 14, 15 16 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 29 30, 31, 32 33 34, 35, 36 37 38, 39, 40 42, 43 44 45 46 47 Name LF1, LF0 ISET VEE NV1, NV0 VCC MR CLK0 nCLK0 OE_REF CLK1 SEL1, SEL0 CLK2 Type Analog Input/Output Analog Input/Output Power Input Power Input Input Input Input Input Input Input
XOIN12:XOIN1
Input
Pulldown
VCXO PLL input divider control input. LVCMOS/LVTTL interface levels.
XOIN0 NPA2, NPA1, NPA0 VCCA NPB2, NPB1, NPB0 MP VCCO_PECL QA, nQA QB, nQB VCCO_CMOS LOCK VCLK REF_CLK
Input Input Power Input Input Power Output Output Power Output Output Output
VCXO PLL input divider control input. LVCMOS/LVTTL interface levels. LVPECL output divider control for QA/nQA outputs. Pulldown LVCMOS/LVTTL interface levels. Analog supply pin. LVPECL output divider control for QB/nQB outputs. Pulldown LVCMOS/LVTTL interface levels. FemtoClockTM circuit clock multiplication control input. Pulldown When HIGH, selects 28. When LOW, selects 32. LVCMOS/LVTTL interface levels. Output power supply pin for LVPECL clock outputs. Pullup Differential clock output pair. LVPECL interface levels. Differential clock output pair. LVPECL interface levels. Output power supply pin for LVCMOS outputs. Lock detect output. LVCMOS/LVTTL interface levels. VCXO PLL clock output. LVCMOS/LVTTL interface levels. Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
843002CY -31
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4
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
FROM PREVIOUS PAGE)
TABLE 1. PIN DESCRIPTIONS (CONTINUED
Number 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59. 60 61 62, 63 64 Name
Type
Description
XOFB12:XOFB1
Input
Pulldown
VCXO feedback divider control input. LVCMOS/LVTTL interface levels.
XOFB0 XTAL_OUT, XTAL_IN VCCA_XO
Input Input Power
Pullup
VCXO feedback divider control input. LVCMOS/LVTTL interface levels. VCXO crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Analog power supply pin for VCXO.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per LVCMOS output) Input Pullup Resistor Input Pulldown Resistor Output Impedance VCC, VCCA, VCCA_XO, VCCO_CMOS, VCCO_PECL = 3.465V Test Conditions Minimum Typical 4 TBD 51 51 7 Maximum Units pF pF k k
843002CY-31
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5
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
Set the QB/nQB output divider control pins, NPB[2:0] = 010 for divide by 4. This sets the QB/nQB LVPECL output pair for 155.52MHz. 2. T1 to T3. (1.544MHz to two 44.736MHz outputs) Since 44.736MHz is slightly higher than the maximum VCXO output frequency, the FemtoClock circuit will have to be used. Using a pullable 22.368MHz on XTAL_IN/XTAL_OUT, set the VCXO PLL feedback divider pins, XOFB[12:0] to 2796 and the input divider pins, XOIN[12:0] to 193. This multiplies the 1.544MHz reference to 22.368MHz (1.544MHz * 2796/193 = 22.368MHz). Set the FemtoClock multiplication control pin, MP, to 28 which sets the VCO at 626.304MHz. Set the QA/nQA output divider control pins, NPA[2:0] = 101 for divide by 14. This sets the QA/nQA LVPECL output pair for 44.736MHz. Set the QB/nQB output divider control pins, NPB[2:0] = 000 for divide by 1. This sets the QB/nQB LVPECL output pair for 44.736MHz 3. T1 to E1. (1.544MHz to two 2.048MHz outputs) The 2.048MHz output frequency requirement is low enough that the FemtoClock circuit is not required. Only the VCXO stage is used for this frequency translation. Using a pullable 24.576MHz on XTAL_IN/XTAL_OUT, set the VCXO PLL feedback divider pins, XOFB[12:0] to 3072 and the input divider pins, XOIN[12:0] to 193. This multiplies the 1.544MHz reference to 2.048MHz (1.544MHz * 3072/193 = 24.576MHz). Set the VCXO PLL Output Divider control pins, NV[1:0] = 01 for /12. This divides the 24.576MHz VCXO PLL frequency down to 2.048MHz.
SECTION 1. FREQUENCY TRANSLATION
The ICS843002-31 is a two stage device, a VCXO PLL stage followed by a low phase noise FemtoClock multiplier stage. The VCXO uses a pullable crystal to lock to the reference clock and can provide an output frequency up to 25MHz on the single-ended VCLK output. For higher frequencies, the low phase noise FemtoClock can multiply the VCXO PLL output clock up to 700MHz on 2 differential LVPECL output pairs (QA/nQA, QB/nQB). The VCXO PLL stage has a 13-bit input divider and a 13-bit feedback divider to generate large integer ratios needed for some frequency translation applications. When configuring the device is to use pullable crystals in the 17.5MHz - 25MHz range on the VCXO PLL stage, and ensure that the FemtoClock PLL is kept within its range of 560MHz to 700MHz. Below are 3 examples: 1. 8kHz to 622.08MHz and 155.52MHz This frequency translation requires use of both the VCXO PLL and the FemtoClock circuit. The VCXO PLL can be used to multiply up to 19.44MHz for use as a reference clock for the FemtoClock which will do the multiplication from 19.44MHz to 622.08MHz. Using a 19.44MHz pullable crystal on XTAL_IN/ XTAL_OUT, set the VCXO PLL feedback divider pins, XOFB[12:0], to 2430. This multiplies the 8kHz reference clock to 19.44MHz. Set the FemtoClock multiplication control pin, MP, to 0 which sets the multiplication factor to 32. This sets the FemtoClock VCO to 622.08MHz. Set the QA/nQA output divider control pins, NPA[2:0] = 000 for divide by 1. This sets the QA/nQA LVPECL output pair for 622.08MHz.
SECTION 2. FREQUENCY CONFIGURATION
The Frequency Configuration Table Examples (see the following pages) are intended to show the most common frequency translation requirements. It is sorted in order of descending input frequency. It is not intended to be an exhaustive configuration table because that would be impractical with almost 3 billion possible configurations. As far as configuration is concerned, frequencies <= 25MHz can be generated with the VCXO PLL while frequencies > 25MHz require the use of the downstream FemtoClock which can multiply the VCXO PLL output up to 700MHz. Complex integer ratios are handled with the VCXO PLL stage and the FemtoClock circuit can be configured to multiply the VCXO PLL output by 32 or 28. The following example will illustrate the configuration process. Assume you have a 1.544MHz T1 clock which needs to be multiplied up to 622.08MHz (OC12). Obviously, the FemtoClock multiplier will be needed to achieve 622.08MHz. Since the FemtoClock has a selectable multiplication factor
843002CY -31
of 28 or 32, this means there are 2 viable VCXO PLL crystal choices which fall within its 17.5MHz - 15MHz range: 22.217143MHz (/28 feedback divider) or 19.44MHz (/32 feedback divider). Use of the /28 feedback divider for the FemtoClock multiplier will give slightly better phase noise, but in this case 22.217143/1.544 cannot be exactly achieved with the 13-bit input and feedback VCXO PLL dividers. Using the x32 setting of the FemtoClock allows a ratio of 19.44/1.544 = 2430/193 which is easily achievable. So the FemtoClock would be set for x32 and a 19.44MHz crystal would be used. The VCXO PLL input divider would be set for 193 and the VCXO PLL feedback divider would be set for 2430. To double check the solution, perform the following calculation: 1.544 * 2430 * 32/193 = 622.08MHz. The 2nd FemtoClock multiplier output, QB/nQB, can be set to equal the QA/nQA output frequency or a fraction of its frequency. The following fractional values are available: /1, /2, /4, /8.
REV. B NOVEMBER 22, 2005
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6
843002CY-31
TABLE 3A. FREQUENCY CONFIGURATION EXAMPLES,
CONTINUED ON NEXT PAGE
Input Frequency (MHz) Application 622.08 -> 622.08 (OC12) 622.08 -> 311.04 (SONET) 622.08 -> 155.52 (OC12 to OC3) 622.08 -> 77.76 (SONET) 622.08 -> 51.84 (OC12 to OC1) 622.08 -> 38.88 (SONET) 622.08 -> 19.44 (SONET) 622.08-> 44.736 (OC12 to T3) 622.08 -> 34.368 (OC12 to E3) 622.08 -> 32.064 (OC12 to J3) 622.08 -> 2.048 (OC12 to E1) 622.08 -> 1.544 (OC12 to T1/J1) 2 4 8 12 16 N/A 622.08 622.08 28 N/A N/A 12 16 N/ A 1 1 8 8 8 1 1 1 N/A N/A N/A 1 N /A N/A N/A 32 32 32 32 N/A 32 626.304 N/A N/ A N/A N/A 622.08 622.08 622.08 622.08 N/A 622.08 N/ A 1 1 14 N/ A N/A N/A N/ A 4 8 12 16 N/A 2 311.04 -> 311.04 (SONET) 311.04 -> 155.52 (SONET) 311.04 -> 77.76 (SONET) 311.04 -> 51.84 (SONET) 311.04 -> 38.88 (SONET) 311.04 -> 19.44 (SONET) 311.04 -> 622.08 (SONET) 311.04 -> 622.08 (SONET) 311.04 -> 44.736 (SONET to T3) 311.04 -> 34.368 (SONET to E3) 311.04 -> 32.064 (SONET to J3) 311.04 -> 2.048 (SONET to E1) 311.04 -> 1.544 (SONET to T1/J1) 155.52 -> 155.52 (OC3) 155.52 -> 77.76 (SONET) 155.52 -> 51.84 (OC3 to OC1) 155.52 -> 38.88 (SONET) 155.52 -> 19.44 (SONET) 155.52 -> 311.04 (SONET) 19.44 19.44 19.44 19.44 19.44 19.44 19.44 22.368 34.368 32.064 24.576 24.704 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 22.368 34.368 32.064 24.576 24.704 19.44 19.44 19.44 19.44 19.44 19.44 8 8 8 1 2430 193 405 32 1620 167 1 1620 179 1 3240 233 1 16 1 1 32 16 1 1 32 16 1 1 N/A 16 1 N/A 32 16 1 N/ A 32 622.08 622.08 16 1 N/A 32 622.08 16 1 N/A 32 622.08 16 1 N/A 32 622.08 4860 193 16 N/A N/A N/A 405 16 12 N/A N/A N/A 3240 167 1 N/A N /A N/A 3240 179 1 N/A N/A N/A 6480 233 N/A 28 626.304 14 32 1 1 N/A N/A N/A 32 1 N/A 32 622.08 16 32 1 N/A 32 622.08 12 32 1 N/A 32 622.08 8 32 1 N/A 32 622.08 4 32 1 N/A 32 622.08 2 32 1 N/A 32 622.08 1
Output Frequency (MHz)
VCXO or FemtoClock Output
Required VCXO Crystal Frequency (MHz)
VCXO Input Divider
VCXO Feedback Divider
VCXO Output Divider
FemtoClock TM ultiplication M Factor
FemtoClock Output Frequency (MHz)
FemtoClock Output Divider
622.08
622.08
FemtoClock Output
622.08
311.04
FemtoClock Output
622.08
155.52
FemtoClock Output
622.08
77.76
FemtoClock Output
Integrated Circuit Systems, Inc.
622.08
51.84
FemtoClock Output
622.08
38.88
FemtoClock Output
622.08
19.44
VCXO Output
622.08
44.736
FemtoClock Output
622.08
34.368
VCXO Output
622.08
32.064
VCXO Output
622.08
2.048
VCXO Output
622.08
1.544
VCXO Output
311.04
311.04
FemtoClock Output
311.04
155.52
FemtoClock Output
PRELIMINARY
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700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
7
311.04
77.76
FemtoClock Output
311.04
51.84
FemtoClock Output
311.04
38.88
FemtoClock Output
311.04
19.44
VCXO Output
311.04
622.08
FemtoClock Output
311.04
622.08
FemtoClock Output
311.04
44.736
FemtoClock Output
311.04
34.368
VCXO Output
311.04
32.064
VCXO Output
311.04
2.048
VCXO Output
311.04
1.544
VCXO Output
155.52
155.52
FemtoClock Output
155.52
77.76
FemtoClock Output
155.52
51.84
FemtoClock Output
155.52
38.88
FemtoClock Output
155.52
19.44
VCXO Output
ICS843002-31
REV. B NOVEMBER 22, 2005
155.52
311.04
FemtoClock Output
843002CY -31
TABLE 3A. FREQUENCY CONFIGURATION EXAMPLES,
CONTINUED ON NEXT PAGE
Input Frequency (MHz) VCXO Feedback Divider Application 155.52 -> 622.08 (OC3 to OC12) 155.52 -> 44.736 (OC3 to T3) 155.52 -> 34.368 (OC3 to E3) 155.52 -> 32.064 (OC3 to J3) 155.52 -> 2.048 (OC3 to E1) 155.52 -> 1.544 (OC3 to T1/J1) 77.76 -> 77.76 (SONET) 77.76 -> 51.84 (SONET) 77.76 -> 38.88 (SONET) 77.76 -> 19.44 (SONET) 77.76 -> 155.52 (SONET) 77.76 -> 311.04 (SONET) 2 1 14 N/A N/A N/A N/A 622.08 622.08 N/A 32 32 N/A N/ A 233 179 167 135 405 2 64 193 1 N/A 1 1 12 16 1 32 32 28 N/A N/A N/A N/A 28 N/A 622.08 622.08 622.08 622.08 626.304 N/A N/A N/A N/A 626.304 N/A N/A 12 16 N/ A 8 4 2 1 14 N/A N/A N/A N/A 14 77.76 -> 622.08 (SONET) 77.76 -> 44.736 (SONET to T3) 77.76 -> 34.368 (SONET to E3) 77.76 -> 32.064 (SONET to J3) 77.76 -> 2.048 (SONET to E1) 77.76 -> 1.544 (SONET to T1/E1) 51.84 -> 51.84 (SONET) 51.84 -> 38.88 (SONET) 51.84 -> 19.44 (SONET) 51.84 -> 77.76 (SONET) 51.84 -> 155.52 (OC1 to OC3) 51.84 -> 311.04 (SONET) 51.84 -> 622.08 (OC1 to OC12) 51.84 -> 44.736 (OC1 to T3) 51.84 -> 34.368 (OC1 to E3) 51.84 -> 32.064 (OC1 to J3) 270 51.84 -> 2.048 (OC1 to E1) 51.84 -> 1.544 (OC1 to T1/J1) 44.736 -> 44.736 (T3) 1 233 179 167 64 193 1 1 1 1 1 1 1 233 179 167 128 386 3 3 3 3 3 3 3 N /A N/A 1 N/A 32 N/A 32 16 N/A 12 N/ A 1 N/A N/A 1 N/A N/A N/A 28 626.304 N/A 32 622.08 N/A 32 622.08 N/A 32 622.08 4 1 N/A N/A N/A N/A 32 622.08 16 N/A 32 622.08 12 N/A 32 622.08 8 16 N/A N/A N/A 12 N/ A N/A N/A 1 N/A N/A N/A 1 N/A N/A N/A N/A 28 626.304 14 N/A 32 622.08 1 VCXO Output Divider FemtoClock TM ultiplication M Factor 19.44 22.368 34.368 32.064 24.576 24.704 19.44 19.44 19.44 19.44 19.44 19.44 19.44 22.368 34.368 32.064 24.576 24.704 19.44 19.44 19.44 19.44 19.44 19.44 19.44 22.368 34.368 32.064 24.576 24.704 22.368 270 540 8 8 8 8 8 8 8 1215 405 405 405 810 4 4 4 4 4 4 4 1215 405 810 810 1620 8
Output Frequency (MHz)
VCXO or FemtoClock Output
Required VCXO Crystal Frequency (MHz)
VCXO Input Divider
FemtoClock Output Frequency (MHz) FemtoClock Output Divider
155.52
622.08
FemtoClock Output
155.52
44.736
FemtoClock Output
155.52
34.368
VCXO Output
155.52
32.064
VCXO Output
Integrated Circuit Systems, Inc.
155.52
2.048
VCXO Output
155.52
1.544
VCXO Output
77.76
77.76
FemtoClock Output
77.76
51.84
FemtoClock Output
77.76
38.88
FemtoClock Output
77.76
19.44
VCXO Output
77.76
155.52
FemtoClock Output
77.76
311.04
FemtoClock Output
77.76
622.08
FemtoClock Output
PRELIMINARY
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700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
8
77.76
44.736
FemtoClock Output
77.76
34.368
VCXO Output
77.76
32.064
VCXO Output
77.76
2.048
VCXO Output
77.76
1.544
VCXO Output
51.84
51.84
FemtoClock Output
51.84
38.88
FemtoClock Output
51.84
19.44
VCXO Output
51.84
77.76
FemtoClock Output
51.84
155.52
FemtoClock Output
51.84
311.04
FemtoClock Output
51.84
622.08
FemtoClock Output
51.84
44.736
FemtoClock Output
51.84
34.368
VCXO Output
51.84
32.064
VCXO Output
51.84
2.048
VCXO Output
51.84
1.544
VCXO Output
ICS843002-31
REV. B NOVEMBER 22, 2005
44.736
44.736
FemtoClock Output
843002CY-31
TABLE 3A. FREQUENCY CONFIGURATION EXAMPLES,
CONTINUED ON NEXT PAGE
Input Frequency (MHz) VCXO Feedback Divider Application 44.736 -> 1.544 (T3 to T1/J1) 44.736 -> 2.048 (T3 to E1) 44.736 -> 19.44 (T3 to SONET) 44.736 -> 32.064 (T3 to J3) 44.736 -> 34.368 (T3 to E3) 44.736 -> 38.88 (T3 to SONET) 44.736 -> 51.84 (T3 to OC1) 44.736 -> 77.76 (T3 to SONET) 44.736 -> 155.52 (T3 to OC3) 44.736 -> 311.04 (T3 to SONET) 44.736 -> 622.08 (T3 to OC12) 38.88 -> 38.88 (SONET) 38.88 -> 19.44 (SONET) 8 4 2 1 626.304 N/A N/ A N/A N/A N/A N/A 1 405 128 386 1 167 334 1 179 233 1 12 16 1 1 N/A 28 N/A N/A N/A N/A N/A N/A 28 N/A N/A N/A 626.304 N/A N/A N/A N/A N/A N/A 626.304 14 N/A N/A N/A N/A N/A 14 N/A N/A N/A N/A N/A N/A 14 38.88 -> 77.76 (SONET) 38.88 -> 155.52 (SONET to OC3) 38.88 -> 311.04 (SONET) 38.88 -> 622.08 (SONET to OC12) 38.88 -> 44.736 (SONET to T3) 38.88 -> 34.368 (SONET to E3) 38.88 -> 32.064 (SONET TO J3) N/A 38.88 -> 2.048 (SONET to E1) 38.88 ->1.544 (SONET to DS1/J1) 34.368 -> 34.368 (E3) 34.368 > 44.736 (E3 to T3) 34.368 -> 32.064 (E3 to J3) 34.368 -> 19.44 (E3 to SONET) 34.368 -> 2.048 (E3 to E1) 34.368 -> 1.544 (E3 to T1) 32.064 -> 32.064 (J3) 32.064 -> 34.368 (J3 to E3) 32.064 -> 44.736 (J3 to T3) 386 128 405 167 179 405 405 405 405 405 405 1 1 1 1 1 1 233 358 334 256 772 1 233 167 1 16 12 1 1 N/ A N/A 28 N/A 32 N/A 32 622.08 622.08 N/A 32 622.08 N/A 32 622.08 1 N/A N/A N/A N/A 32 622.08 16 N/A 32 622.08 1 N/A 32 622.08 2 N/A 32 622.08 4 N/A 32 622.08 8 N/A 32 622.08 12 N/A 32 622.08 16 1 N/A N/A N/A 1 N/A N/A N/A 1 N/A N/A N/A 12 N/A N/A N/A 16 N/A N/A N/A VCXO Output Divider FemtoClock TM ultiplication M Factor 24.704 24.576 19.44 32.064 34.368 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 22.368 34.368 32.064 24.576 24.704 34.368 22.368 32.064 19.44 24.576 24.704 32.064 34.368 22.368 537 17 9 716 179 358 1 1215 405 405 405 40 5 2 2 2 2 2 2 932 932 932 932 932 932 233 233 932 233 699
Output Frequency (MHz)
VCXO or FemtoClock Output
Required VCXO Crystal Frequency (MHz)
VCXO Input Divider
FemtoClock Output Frequency (MHz) FemtoClock Output Divider
44.736
1.544
VCXO Output
44.736
2.048
VCXO Output
44.736
19.44
VCXO Output
44.736
32.064
VCXO Output
Integrated Circuit Systems, Inc.
44.736
34.368
VCXO Output
44.736
38.88
FemtoClock Output
44.736
51.84
FemtoClock Output
44.736
77.76
FemtoClock Output
44.736
155.52
FemtoClock Output
44.736
311.04
FemtoClock Output
44.736
622.08
FemtoClock Output
38.88
38.88
FemtoClock Output
38.88
19.44
VCXO Output
PRELIMINARY
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700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
9
38.88
77.76
FemtoClock Output
38.88
155.52
FemtoClock Output
38.88
311.04
FemtoClock Output
38.88
622.08
FemtoClock Output
38.88
44.736
FemtoClock Output
38.88
34.368
VCXO Output
38.88
32.064
VCXO Output
38.88
2.048
VCXO Output
38.88
1.544
VCXO Output
34.368
34.368
VCXO Output
34.368
44.736
FemtoClock Output
34.368
32.064
VCXO Output
34.368
19.44
VCXO Output
34.368
2.048
VCXO Output
34.368
1.544
VCXO Output
32.064
32.064
VCXO Output
32.064
34.368
VCXO Output
ICS843002-31
REV. B NOVEMBER 22, 2005
32.064
44.736
FemtoClock Output
843002CY -31
TABLE 3A. FREQUENCY CONFIGURATION EXAMPLES,
CONTINUED ON NEXT PAGE
Input Frequency (MHz) Application 32.064 -> 2.048 (J3 to E1) 32.064 -> 1.544 (J3 to T1) 19.44 -> 19.44 (SONET) 19.44 -> 38.88 (SONET) 19.44 -> 51.84 (SONET to OC1) 19.44 -> 77.76 (SONET) 19.44 -> 155.52 (SONET to OC3) 19.44 -> 311.04 (SONET) 19.44 -> 622.08 (SONET to OC12) 19.44 -> 44.736 (SONET to T3) 19.44 -> 34.368 (SONET to E3) 19.44 -> 32.064 (SONET to J3) 19.44 -> 2.048 (SONET to E1) N/A 1 1 1 N/A N/A N/A N/A 28 N/A N/A 1 1 2796 3088 3072 1 1 2430 4008 N/A 16 12 1 1 N/A N/A 28 N/A N/A N/A N/A 626.304 N/A N/A N/A N/A 626.304 N/A N/A N/A N/A N/A N/A N/A N/A 14 N/A N/A N/A N/A 14 N/A N/ A N/A N/A 19.44 -> 1.544 (SONET to T1/J1) 19.44 -> 666.5142857 (255/238 FEC) 19.44 -> 669.3265823 (255/237 FEC) 19.44 -> 672.1627119 (255/236 FEC) 2.048 -> 2.048 (E1) 2.048 -> 1.544 (E1 toT1/J1) 2.048 -> 34.368 (E1 to E3) 2.048 -> 32.064 (E1 to J3) 2.048 -> 44.736 (E1 to T3) 1.544 -> 1.54 (T1/J1) 1.544 -> 2.048 (T1 to E1) 1.544 -> 32.064 (T1/J1 to J3) 1.544 -> 34.368 (T1/J1 to E3) 1.544 -> 44.736 (T1/J1 to T3) 8KHz -> 1.544MHz (Frame Clock to T1) 8KHz -> 2.048MHz (Frame Clock to E1) 8KHz -> 19.44MHz (Frame Clock to SONET) 8KHz -> 32.064MHz (Frame Clock to J3) 24.576 24.704 19.44 19.44 19.44 19.44 19.44 19.44 19.44 22.368 34.368 32.064 24.576 24.704 16 N/A N/A N/A 12 16 1 1 N/A 16 12 N/A N/A N/A N/A 32 32 669.3265823 672.1627119 32 666.5142857 N/A N/A 20.82857143 20.9164557 21.00508475 24.576 24.704 34.368 32.064 22.368 24.704 24.576 32.064 34.368 22.368 24.704 24.576 19.44 32.064 1 1 193 193 4296 193 4008 193 3072 1 16 64 699 32 501 32 537 16 193 1 12 236 255 79 85 14 15 1215 1544 405 512 12 N/A N/A N/A 405 668 1 N/A N/A N/A 405 716 1 N/A N/A N/A 405 466 N/A 28 626.304 14 1 1 N/A 32 622.08 1 1 1 N/A 32 622.08 2 1 1 N/A 32 622.08 4 1 1 N/A 32 622.08 8 1 1 N/A 32 622.08 12 1 1 N/A 32 622.08 16 1 1 1 N/A N/A N/A 501 386 16 N/A N/A N/A 167 128 12 N/A N/A N/A
Output Frequency (MHz)
VCXO or FemtoClock Output
Required VCXO Crystal Frequency (MHz) VCXO Input Divider VCXO Feedback Divider FemtoClock Output Divider VCXO Output Divider FemtoClock TM ultiplication M Factor
FemtoClock Output Frequency (MHz)
32.064
2.048
VCXO Output
32.064
1.544
VCXO Output
19.44
19.44
VCXO Output
19.44
38.88
FemtoClock Output
Integrated Circuit Systems, Inc.
19.44
51.84
FemtoClock Output
19.44
77.76
FemtoClock Output
19.44
155.52
FemtoClock Output
19.44
311.04
FemtoClock Output
19.44
622.08
FemtoClock Output
19.44
44.736
FemtoClock Output
19.44
34.368
VCXO Output
19.44
32.064
VCXO Output
19.44
2.048
VCXO Output
19.44
1.544
VCXO Output
PRELIMINARY
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700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
10
19.44
666.5142857
FemtoClock Output
19.44
669.3265823
FemtoClock Output
19.44
672.1627119
FemtoClock Output
2.048
2.048
VCXO Output
2.048
1.544
VCXO Output
2.048
34.368
VCXO Output
2.048
32.064
VCXO Output
2.048
44.736
FemtoClock Output
1.544
1.544
VCXO Output
1.544
2.048
VCXO Output
1.544
32.064
VCXO Output
1.544
34.368
VCXO Output
1.544
44.736
FemtoClock Output
0.008
1.544
VCXO Output
0.008
2.048
VCXO Output
0.008
19.44
VCXO Output
ICS843002-31
REV. B NOVEMBER 22, 2005
0.008
32.064
VCXO Output
843002CY-31
TABLE 3A. FREQUENCY CONFIGURATION EXAMPLES
Required VCXO Crystal Frequency (MHz) VCXO Input Divider VCXO Feedback Divider Application 8KHz -> 34.368MHz (Frame Clock to E3) 8KHz -> 44.736MHz (Frame Clock to T3) 8KHz -> 38.88MHz (Frame Clock to SONET) 8KHz -> 77.76MHz (Frame Clock to SONET) 8KHz ->155.52MHz (Frame Clock to OC3) 8KHz -> 311.04MHz (Frame Clock to SONET) 8KHz -> 622.08MHz (Frame Clock to OC12) 4296 2796 2430 N/ A N/A N/ A N/ A N/A 32 622.08 1 32 622.08 2 32 622.08 4 32 622.08 8 32 622.08 16 2430 2430 2430 2430 1 28 626.304 14 1 N/A N/A N/A VCXO Output Divider FemtoClock TM ultiplication M Factor FemtoClock Output Divider 1 1 1 1 1 1 1 FemtoClock Output Frequency (MHz) 34.368 22.368 19.44 19.44 19.44 19.44 19.44
Input Frequency (MHz)
Output Frequency (MHz)
VCXO or FemtoClock Output
0.008
34.368
VCXO Output
0.008
44.736
FemtoClock Output
0.008
38.88
FemtoClock Output
0.008
77.76
FemtoClock Output
Integrated Circuit Systems, Inc.
0.008
155.52
FemtoClock Output
0.008
311.04
FemtoClock Output
0.008
622.08
FemtoClock Output
PRELIMINARY
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700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
11
ICS843002-31
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
4.6V -0.5V to VCC + 0.5V -0.5V to VCCO + 0.5V 50mA 100mA 22.3C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO (LVCMOS) Outputs, IO (LVPECL) Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_CMOS = VCCO_PECL = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA, VCCA_XO VCCO_CMOS, VCCO_PECL IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 395 15 Maximum 3.465 3.465 3.465 Units V V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_CMOS = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage MP, MR, OE_REF, SEL0, SEL1, XOIN[12:1], NPA[2:0], NPB[2:0], Input CLK1, CLK2, XOFB[12:1] High Current NV0, NV1, XOIN0, XOFB0 MP, MR, OE_REF, SEL0, SEL1, XOIN[12:1], NPA[2:0], NPB[2:0], Input CLK1, CLK2, XOFB[12:1] Low Current NV0, NV1, XOIN0, XOFB0 Output High Voltage Output Low Voltage REF_CLK, VCLK, LOCK; NOTE 1 REF_CLK, VCLK, LOCK; NOTE 1 Test Conditions Minimum 2 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 2.6 0.5 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A V V
IIL
VOH VOL
NOTE 1: Outputs terminated with 50 to VCCO_CMOS/2.
843002CY -31
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12
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
Test Conditions CLK0 nCLK0 CLK0 nCLK0 VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -150 -5 0.15 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_CMOS = VCCO_PECL = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VCC + 0.3V.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_PECL = 3.3V5%, TA = 0C TO 70C
Symbol Parameter VOH VOL Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 Typical Maximum VCCO - 0.9 VCCO - 1.7 Units V V V
VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 NOTE 1: Outputs terminated with 50 to VCCO_PECL - 2V. See "Parameter Measurement Information" section, "3.3V Output Load Test Circuit".
TABLE 5. CRYSTAL CHARACTERISTICS
Symbol fN fT fS CL CO CO/C1 ESR Parameter Nominal Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio Equivalent Series Resistance Drive Level Mode of Operation Fundamental 0 12 4 220 240 50 1 mW Test Conditions Minimum Typical 19.44 TBD TBD 70 Maximum Units MHz ppm ppm C pF pF
843002CY-31
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13
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
Test Conditions Minimum 35 4.375 1.1875 Random jitter Deterministic jitter Total jitter Random jitter Deterministic jitter Total jitter Random jitter Deterministic jitter Total jitter Random jitter Deterministic jitter Total jitter CLK0/nCLK0 = 19.44MHz QA/B = 77.76MHz VCLK = REF_CLK = 19.44MHz; NOTES 1, 2, 4 CLK1/2 = 8kHz QA/B = 77.76MHz VCLK = REF_CLK = 19.44MHz; NOTES 1, 3, 5 20% to 80% 1.3 0.75 1.5 3.5 1 0.5 1.1 0.7 1 0.3 1.1 2.7 0.9 0.19 0.9 0.6 2 2 2.5 1 1.5 3 200 50 50 700 Typical Maximum 700 700 25 200 Units MHz MHz MHz MHz ps ps ps mUI ps ps ps mUI ps ps ps mUI ps ps ps mUI ns ns ns ns ns ns ps % % ms
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_CMOS = VCCO_PECL = 3.3V5%, TA = 0C TO 70C
Symbol Parameter QA/nQA fOUT Output Frequency QB/nQB VCLK REF_CLK OC-48 mask (12kHz - 20MHz) 19.44MHz input, into CLK0 622.08MHz output; NOTE 1, 2 OC-12 mask (250kHz - 5MHz) 19.44MHz input, into CLK0 155.52MHz output; NOTE 1, 3
t(J)
Timing Jitter OC-48 mask (12kHz - 20MHz) 8kHz input, into CLK2 622.08MHz output; NOTE 1, 2 OC-12 mask (250kHz - 5MHz) 8kHz input, into CLK2 155.52MHz output; NOTE 1, 3 CLK0/nCLK0 to (QA or QB) CLK0/nCLK0 to VCLK Input to Output Clock Skew (rising clock edge) CLK0/nCLK0 to REF_CLK CLK1 or CLK2 to QA or QB CLK1 or CLK2 to VCLK CLK1 or CLK2 to REF_CLK
t(IO)
t R / tF odc
Output Rise/Fall Time Output Duty Cycle QA/QB @ 622.08MHz VCLK, REF_CLK @ 19.44MHz
PLL Lock Time 100 tLOCK See Parameter Measurement Information section. NOTE 1: External crystal is 19.44MHz Eliptek ECX-5451. NOTE 2: Loop bandwidth (-3dB) = 180Hz; Loop Damping Factor = 5.3 (see Applications Section, Example Loop Filter Component Value, example case #4). NOTE 3: Loop bandwidth (-3dB) = 19Hz; Loop Damping Factor = 2.8 (see Applications Section, Example Loop Filter Component Value example case #2). NOTE 4: XOIN = XOFB = NPA = NPB = /8, MP = 0 (x32); NV = /1. NOTE 5: XOIN = 1; XOFB = 2430; NPA = NPB = /8, MP = 0 (x32); NV = /1.
843002CY -31
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14
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
2V 1.65V 5%
V CC , VCCA, VCCA_XO, VCCO_PECL
Qx
SCOPE
VCC , VCCA, VCCA_XO, VCCO_CMOS
Qx
SCOPE
LVPECL
VEE
nQx
LVCMOS
VEE
-1.3V 0.165V
-1.65V 5%
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
nQA
V
DDO
QA nQB
VCLK
2
V
DDO
QB
REF_CLK
tsk(o)
2 tsk(o)
LVPECL OUTPUT SKEW
LVCMOS OUTPUT SKEW
nQA, nQB QA, QB VCLK, REF_CLK
t
PERIOD
V
CCO_LVCMOS
2
t PW
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
odc =
t PW t PERIOD
x 100%
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
843002CY-31
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
REV. B NOVEMBER 22, 2005
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15
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
Phase Noise Plot
Noise Power
Phase Noise Mask
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
PHASE JITTER
LVPECL OUTPUT RISE/FALL TIME
80% 20% tR
80% 20% tF
Clock Outputs
LVCMOS OUTPUT RISE/FALL TIME
843002CY -31
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16
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR APPLICATION INFORMATION
DESCRIPTION OF THE PLL STAGES
The ICS843002-31 is a two stage frequency multiplication device, a VCXO PLL followed by a low phase noise FemtoClock frequency multiplier. The VCXO uses an external pullable crystal which can be pulled 100ppm by the VCXO PLL circuitry to phase lock it to the input reference frequency. The output frequency of the VCXO PLL is equal to that of the external pullable crystal, which is in the range of 17.5MHz to 25MHz. The loop bandwidth VCXO PLL is typically set in the range of 10-250Hz which provides attenuation of input reference clock jitter. Since the VCXO is a high-Q oscillator circuit, it has low intrinsic output jitter and phase noise. The VCXO PLL output clock is available from the VCLK pin. The FemtoClock frequency multiplier has an effective control bandwidth of about 800kHz which means it will track the VCXO PLL clock output. The above equation calculates the "normalized" loop bandwidth (denoted as "NBW") which is approximately equal to the - 3dB bandwidth. NBW does not take into account the effects of damping factor or the second pole imposed by CP. It does, however, provide a useful approximation of filter performance. To prevent jitter on VCLK due to modulation of the VCXO PLL by the phase detector frequency, the following general rule should be observed: NBW (VCXO PLL) (Phase Detector) 20
(Phase Detector) = Input Frequency / XOIN The PLL loop damping factor (DF) is determined by: RS 2 ICP x CS x KO XOFB Divider
VCXO PLL LOOP RESPONSE CONSIDERATIONS
Loop response characteristics of the VCXO PLL is affected by the setting of the VCXO feedback divider value (XOFB) and by the external loop filter components. A practical range of loop bandwidth for many applications is 25Hz to 1kHz. A bandwidth of less than 10Hz requires careful component selection and possible metal shielding to prevent clock output wander. A damping factor of 0.7 or greater should be used to ensure loop stability. When a passband peaking of <0.1dB is desired for SONET/SDH loop timing application, the damping factor should be 6 or higher. A PC base PLL bandwidth calculator is also under development. For assistance with loop filter bandwidth and component selection suggestions, please contact your ICS sales representative. DF (VCLK) =
x
WHERE: CS = Value of capacitor CS in loop filter in farads
optional
optional
LFR LF CP RS CS ISET
64 1 2 3
63
62
SETTING THE VCXO PLL LOOP RESPONSE
The VCXO PLL loop response is determined both by fixed device characteristics and by other characteristics set by the user. This includes the values of RS, CS, CP and RSET as shown in the External VCXO PLL Components figure on this page. The VCXO PLL loop bandwidth is approximated by: NBW (VCXO PLL) = RS x ICP x KO 2 x XOFB Divider
RSET
FIGURE 1. EXTERNAL VCXO PLL COMPONENTS
WHERE: RS = Value of resistor RS in loop filter in ohms ICP = Charge pump current in amps (see table on page 17) KO = VCXO Gain in Hz/V (see table on page 18) XOFB Divider = 1 to 8191
843002CY-31
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17
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
NOTES ON EXTERNAL CRYSTAL LOAD CAPACITORS
In the loop filter schematic diagram, capacitors are shown from pin 62 to ground and pin 63 to ground. These are optional crystal load capacitors which can be used to center tune the external pullable crystal (the crystal frequency can only be lowered by adding capacitance, it cannot be raised). Note that the addition of external load capacitors will decrease the crystal pull range and the Kvco value.
NOTES ON SETTING THE VALUE OF CP
As another general rule, the following relationship should be maintained between components CS and CP in the loop filter: CP = CS 20
CP establishes a second pole in the VCXO PLL loop filter. For higher damping factors (> 1), calculate the value of CP based on a CS value that would be used for a damping factor of 1. This will minimize baseband peaking and loop instability that can lead to output jitter. CP also dampens VCXO PLL input voltage modulation by the charge pump correction pulses. A CP value that is too low will result in increased output phase noise at the phase detector frequency due to this. In extreme cases where input jitter is high, charge pump current is high, and CP is too small, the VCXO PLL input voltage can hit the supply or ground rail resulting in non-linear loop response. The best way to set the value of CP is to use the filter response software available from ICS (please refer to the following section). CP should be increased in value until it just starts affecting the passband peak.
LOOP FILTER RESPONSE SOFTWARE
Online tools to calculate loop filter response can be found at www.icst.com.
NOTES ON SETTING CHARGE PUMP CURRENT
The recommended range for the charge pump current is 50A to 500A. Below 50A, loop filter charge leakage, due to PCB or capacitor leakage, can become a problem. This loop filter leakage can cause locking problems, output clock cycle slips, or low frequency phase noise. As can be seen in the loop bandwidth and damping factor equations or by using the filter response software available from ICS, increasing charge pump current (ICP) increases both bandwidth and damping factor.
1E-3
CHARGE PUMP CURRENT, EXAMPLE SETTINGS
RSET 17.6K 8.8K 4.4K 2.2K Charge Pump Current (ICP) 62.5A 125A 250A 500A
ICP, Amps
100E-6
10E-6 1k 10k RSET, 100k
FIGURE 2. CHARGE PUMP CURRENT VS. VALUE (EXTERNAL RESISTOR) GRAPH
843002CY -31
OF
RSET
REV. B NOVEMBER 22, 2005
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18
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
VCXO GAIN (KO) VS. XTAL FREQUENCY
9000
8000
K VCO (Hz/V)
7000
6000
5000
4000 16 18 20 22 24 26
XTAL Frequency (MHz)
EXAMPLE LOOP FILTER COMPONENT VALUE
Example Case Number 1 2 3 4 Input Reference Clock 8kHz 8kHz 19.44kHz 19.44MHz Device Configuration XTAL XOIN XOFB Frequency Divider Divider (MHz) 19.44 1 2430 19.44 19.44 19.44 1 32 8 2430 32 8 MP Divider 0 0 0 0 Loop Filter Component Selection RSET RS CS CP Resistor Resistor Cap Cap (k ) (k ) (F) (F) 4.5 150 10 0.01 4.5 9.09 9.09 150 11 11 2.2 10 10 0.01 0.01 0.01 VCXO PLL Performance Loop BW Loop Passband (-3dB) Damping Peaking (MHz) Factor (dB) 18 5.8 0.1 19 65 180 2.8 2.7 5.3 0.3 0.3 0.1
843002CY-31
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19
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
3.3V VCC .01F V CCA .01F 10F 10
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843002-31 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, VCCA_XO, and VCCO_X should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
FIGURE 3. POWER SUPPLY FILTERING
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK0 /nCLK0 accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the HiPerClockS CLK0/nCLK0 input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
3.3V
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V LVDS_Driv er
Zo = 50 Ohm
CLK R1 100 Zo = 50 Ohm
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
843002CY -31
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER
REV. B NOVEMBER 22, 2005
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20
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
DIFFERENTIAL CLOCK INPUT CIRCUIT USING THE DIFFERENTIAL INTERFACE FOR SINGLE-ENDED CLOCKS
The differential interface (CLK0/nCLK0) can be used as a third single-ended input to support an LVCMOS or LVTTL clock driver. The clock input is connected to the CLK0 input pin, and the nCLK0 pin is left unconnected. To help reduce interference with the internal VCO circuits, an external resistor can be placed in series with the clock signal near the CLK0 input pint. Combined with the input pin capacitance, this resistor acts as a low pass signal filter. The typical value of this optional series filter resistor is 100. This will lower both the amplitude and edge rate of the clock input signal. In the case of a very short clock trace a series termination register may not be needed.
Series Termination LVTTL or LVCMOS Logic Output
Optional Series Filter Resistor
3.3V CLK0
3.3V CLK
nCLK0
(no connection)
51k nCLK 51k 51k Differential Input Stage
External Circuitry
Internal Device Circuitry
FIGURE 5. SINGLE-ENDED CLOCK INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
843002CY-31
LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
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21
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
PCB is contacted through solder as shown in Figure 6. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor's Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology.
EXPOSED PAD SOLDER
THERMAL RELEASE PATH
The exposed metal pad provides heat transfer from the device to the P.C. board. The exposed metal pad is ground pad connected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the
SOLDER M ASK SIGNAL TRACE
SIGNAL TRACE
GROUND PLANE THERM AL VIA
Expose Metal Pad (GROUND PAD)
FIGURE 6. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
TERMINATION
FOR
LVPECL OUTPUTS
designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 7A and 7B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 7A. LVPECL OUTPUT TERMINATION
FIGURE 7B. LVPECL OUTPUT TERMINATION
843002CY -31
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22
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002-31. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843002-31 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 395mA = 1368.67mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 1368.67mW + 60mW = 1428.67mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 17.2C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 1.429W * 17.2C/W = 94.6C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA FOR 64-PIN TQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 22.3C/W
200
17.2C/W
500
15.1C/W
843002CY-31
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23
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50) * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843002CY -31
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24
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE FOR 64 LEAD TQFP, EPAD
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 22.3C/W
200
17.2C/W
500
15.1C/W
TRANSISTOR COUNT
The transistor count for ICS843002-31 is: 10,095
843002CY-31
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25
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
PACKAGE OUTLINE - Y SUFFIX FOR 64 LEAD TQFP, EPAD (32 pin package depicted to define Table 9 dimension symbols)
TABLE 9. PACKAGE DIMENSIONS FOR 64 LEAD TQFP, EPAD
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 .95 0.17 0.09 BCD MINIMUM NOMINAL 64 --1.0 0.22 -12.00 BASIC 10.00 BASIC 5.00 Ref. 12.00 BASIC 10.00 BASIC 5.00 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.20 0.15 1.05 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
843002CY -31
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26
REV. B NOVEMBER 22, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSTM VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
Marking Package 64 Lead TQFP, EPAD 64 Lead TQFP, EPAD 64 Lead "Lead-Free" TQFP, EPAD 64 Lead "Lead-Free" TQFP, EPAD Shipping Packaging tray 500 tape & reel tray 500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS843002CY-31 ICS843002CY-31T ICS843002CY-31LF ICS843002CY-31LFT ICS843002CY31 ICS843002CY31 TBD TBD
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843002CY-31
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27
REV. B NOVEMBER 22, 2005

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